Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems

The need for detailed simulation of integrated circuits has received significant attention since the early stages of design automation. Given the increasing device integration, these simulations have extreme memory footprints, especially within unified memory hierarchies. This paper overcomes the infeasible memory demands of modern circuit simulators. Structural partitioning of the netlist and temporal partitioning of the input signals allow distributed execution with minimal memory requirements. The proposed framework is validated with simulations of a circuit with more than 10 MOSFET devices. In comparison to a commercial tool, we observe minimal error and even ×2.35 speedup for moderate netlist sizes. The proposed framework is proven highly reusable across a variety of execution platforms.